Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers

This work presents novel multipliers for Montgomery multiplication defined on binary fields GF(2). Different to state of the art Montgomery multipliers, this work uses a Linear Feedback Shift Register (LFSR) as the main building block. We studied different architectures for bit-serial and digit-serial Montgomery multipliers using the LFSR and the Montgomery factors x and x. The proposed multipliers are for different classes of irreducible polynomials: general, all one polynomials (AOP), pentanomials and trinomials. The results show that the use of LFSRs simplifies the design of the multipliers architecture reducing area resources and retaining high performance compared to related works.